This invention relates to a digital temperature sensor (DTS) system to monitor temperature in a memory subsystem, and particularly one capable of monitoring both ambient air or packaging surface temperature at multiple locations in a coupled commercial DRAM memory array.
The present inventions were created in a development directed to using commercial memory products to be used with a memory interface for IBM products. Representative of the commercial memories is the memory of Samsung Electronics Co., Ltd""s represented by their DDR-II SDRAM (Synchronous Dynamic Random Access Memory).
As this application is directed to temperature sensing, we note that patents have been granted for temperature sensing of semiconductor chips at multiple locations. Examples of such patents include the U.S. Pat. No. 5,994,752 for a field-effect-controllable semiconductor component with a plurality of temperature sensors, as filed by Rainald Sander and Alfons Graf for the assignee, Siemens Aktiengesellschaft, Munich, Germany. In this U.S. Pat. No. 5,994,752 issued Nov. 30, 1999 a field-effect-controllable power semiconductor component, such as a power MOSFET or IGBT, includes a semiconductor body, at least one cell field, a multiplicity of mutually parallel-connected transistor cells disposed in at least one cell field, and at least two temperature sensors integrated in the semiconductor body and disposed at different locations from each other on the semiconductor body. Thus a temperature gradient between a strongly heated local region of the semiconductor body and one of the temperature sensors is reduced and a response time in the event of an overload is shortened.
U.S. Pat. No. 6,144,085 of Richard J. Parker, issued Nov. 7, 2000 for a power transistor device having hot-location and cool-location temperature sensors, was assigned to U.S. Philips Corporation, New York, N.Y . In this U.S. Pat. No. 6,144,085 a power transistor device, for example a MOSFET or an IGBT, provided a semiconductor chip which accommodates an array of parallel device cells in which heat is generated in operation of the chip device. A hot-location temperature sensor was located inside the array, and a cool-location temperature sensor was located outside the array. Each of these sensors have at least one sensor cell which is of the same transistor type as the device cells. The sensor cells have a cellular region structure similar to that of the device cells, but each sensor has a respective output electrode separate from electrodes of the device cells. A detection circuit is coupled to the respective output electrodes of the hot-location and cool-location temperature sensors for detecting a temperature difference between the hot and cool locations by comparing voltage signals from the output electrodes.
In Shoichi Furuhata""s U.S. Pat. No. 5,521,421 for a semiconductor device issued May 28, 1996 to Fuji Electric Co., Ltd., Hino, Japan, there was described a semiconductor device with a power element on a substrate, and the device had a temperature monitor element formed on the same substrate. In case of thermal overload in the power element, a signal from the temperature monitor element could be used for turning the power element off. For enhanced temperature response, the temperature monitor element was partly surrounded by the power element or/and disposed beneath an integrated, thermally conductive extension of an electrode of the power element.
However, while temperature sensing techniques like those indicated above for semiconductor chips have been known, these prior teachings do not address the need for a digital temperature sensor (DTS) to monitor either ambient air or packaging surface temperature in a memory subsystem when the memory itself is designed by others or is a commercial product, as is the custom today with the use of industry standard components. The temperature inside the commercial memory subsystem can vary over time, and an effective, accurate, and low-cost method is needed to monitor the temperature. In creating this solution, it is also recognized that there are commercial sensing devices which can be mounted in a higher level package, which can be monitored with special hardware, which, however, do not meet the needs to which our invention is directed.
In the related invention an Analog-to-Digital Converter (ADC) is used to monitor Vddq. Here it should be noted that U.S. Pat. No. 5,206,944 for high speed analog to digital converter board for memory applications for an IBM PC/AT has issued Apr. 27, 1993 to inventor Michael D. Pilkenton and assigned to The United States of America as represented by the Secretary of the Air Force, Washington, D.C. In this patent a flash analog-to-digital converter (ADC) was provided in a single IC package which has an analog input coupled to a video signal source. The data line from the ADC circuit goes to a SRAM (Static Random Access Memory) memory made up of four identical banks which are interleaved together so that slower less costly memory chips can be used. In this device an interface circuit provides communication between the computer and a digitizer, with address, data and control lines. The U.S. Pat. No. 5,206,944 digitizer, which comprises integrated circuit cards designed to attach to an expansion slot in an IBM PC/AT, operates at 20 megasamples per second for approximately 52 milliseconds and provides eight bit resolution on the signal input. The computer software includes a device driver for the digitize A sync pulse from the video tape unit which is monitored by a sync pulse input comparator to trigger the start of a digitizing sequence. Thus, we can recognize ADCs have been used in memory interface applications.
Also, some vendors include a Digital Temperature Sensor (DTS) in the same component as the ADC. Examples of this are the Analog Devices, Inc.""s AD7417 and AD 7418, which contain a DTS and either four or one ADC respectively. These devices are not being used to monitor memory subsystem temperatures.
In order to use the representative commercial memory SDRAMs we have achieved a way to allow signals to access a Samsung Electronics Co., Ltd""s DDR-II SDRAM (Synchronous Dynamic Random Access Memory) which includes on-chip registers, described in its specification, which implement a programmable CAS latency, and a programmable additive latency to ensure a tRCDmin specification is met. The present application describes separate inventions described in this application which do not affect or alter the contents of these registers, and do not make use of the contents of the Samsung registers, and yet enable a commercial SDRAM memory such as the Samsung DDR-II SDRAM to be used in a standard memory subsystem for IBM using a new ASIC (application specific integrated circuit).
The preferred embodiment of the invention uses a Digital Temperature Sensor (DTS) system to monitor either ambient air or packaging surface temperature in a memory subsystem which uses a variety of separate coupled commercial memory parts not necessarily manufactured by the creator of the memory subsystem. In accordance with the preferred embodiment of the invention, a Digital Temperature Sensor DTS is connected to an ASIC which serves as a memory controller for the separate coupled memory chips supplied by various commercial vendors of state of the art memory, such as memories meeting standards developed by the JEDEC standards committee and marketed by member supporters of the standards committee, for example the Double Data Rate or DDR memories like those of Samsung Electronics Co., Ltd. as represented by its DDR-II SDRAM (Synchronous Dynamic Random Access Memory).
There have been many improvements to the interface for controlling a memory subsystem comprising plural arrays of SDRAM in the form of a plurality of SDRAM memory chips which are made to operate with a memory subsystem control system utilizing our developments with a new memory controller interface ASIC (application specific integrated circuit). Our system varies Vref during initial adjustment of the pull-up and pull down impedance of a DDR-II SDRAM off-chip data drivers. The system finds an optimum impedance setting for the DDR-II SDRAM off-chip driver pull-up and pull-down impedance during initialization. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref=1/m*Vddq+OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n*Vddq to nxe2x88x921/n*Vddq, where n is the voltage granularity of the DAC.
The overall system monitors surface temperature, ambient air temperature, or both at one or more locations in a memory subsystem using one ASIC and one or more DTS. One or more fans are controlled in order to control as well as monitor surface and ambient air temperature. The memory subsystem has a Built In AC Self Test. This system writes pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. The system varies Vref across its allowable range during Built In AC Self Test to provide improved self-test coverage.
These and other improvements are set forth in the following detailed description so as to enable a clearer understanding of our claimed inventions. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.